1. Field of the Invention
The present invention relates to a metallization method for manufacturing semiconductor devices. More particularly, the present invention relates to fully planarized dual damascene metallization using a copper line interconnect and a selective CVD metal via plug.
2. Background of the Related Art
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (VLSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines or other features. Reliable formation of these interconnect features is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, must decrease. Therefore, there is a great amount of ongoing effort being directed at the formation of smaller and smaller void-free features. One such method involves selective chemical vapor deposition (CVD) of material only on exposed nucleation surfaces as provided on the substrate surface. Selective CVD involves the deposition of a film layer upon contact of a component of the chemical vapor with a conductive substrate. The component nucleates on such substrate creating a metal surface on which further deposition proceeds.
Selective CVD metal deposition is based on the fact that the decomposition of a CVD metal precursor gas usually requires a source of electrons from a conductive nucleation film. In accordance with a conventional selective CVD metal deposition process, the metal should grow in the bottom of an aperture where either a metal film or doped silicon or metal silicide from the underlying conductive layer has been exposed, but should not grow on dielectric surfaces such as the field and aperture walls. The underlying metal films or doped silicon are electrically conductive, unlike the dielectric field and aperture walls, and supply the electrons needed for decomposition of the metal precursor gas and the resulting deposition of the metal. The result obtained through selective deposition is an epitaxial xe2x80x9cbottom-upxe2x80x9d growth of CVD metal in the apertures capable of filling very small dimension ( less than 0.25 xcexcm), high aspect ratio ( greater than 5:1) via or contact openings.
Elemental aluminum (Al) and its alloys have been the traditional metals used to form lines and plugs in semiconductor processing because of aluminum""s low resistivity, superior adhesion to silicon dioxide (SiO2), ease of patterning, and high purity. Furthermore, aluminum precursor gases are available which facilitate the selective CVD process described above. However, aluminum has higher resistivity and problems with electromigration. Electromigration is a phenomenon that occurs in a metal circuit while the circuit is in operation, as opposed to a failure occurring during fabrication. Electromigration is caused by the diffusion of the metal in the electric field set up in the circuit. The metal gets transported from one end to the other after hours of operation and eventually separates completely, causing an opening in the circuit. This problem is sometimes overcome by Cu doping and texture improvement. However, electromigration is a problem that gets worse as the level of integration increases.
Copper and its alloys, on the other hand, have even lower resistivities than aluminum and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. However, the primary problems with integrating copper metal into multilevel metallization systems are (1) the difficulty of patterning the metal using etching techniques, and (2) filling small vias using PVD and lack of CVD process. For devices of submicron minimum feature size, wet etch techniques for copper patterning have not been acceptable due to liquid surface tension, isotropic etch profile, and difficulty in over-etch control. No reliable dry etch process is available.
Several methods have been proposed for producing patterned copper interconnects, including selective electroless plating, selective chemical vapor deposition, high temperature reactive ion etching and lift off processing. Electroless plating requires that the floor of an interconnect be seeded to make the floor conductive. The conductive floor can then be charged to attract copper from a solution or bath.
Selective chemical vapor deposition typically involves the decomposition of a metal precursor gas on an electrically conducting surface. However, a reliable process for selective CVD copper is not available.
High temperature reactive ion etching (RIE), or sputter etching, has also been used to pattern a copper layer. Furthermore, the RIE can be used in conjunction with lift off processing in which excess metal is lifted off the structure by a release layer to leave a planar surface having a copper feature formed therein.
Yet another technique for metal wiring of copper comprises the patterning and etching of a trench via and/or contact within a thick layer of insulating material, such as SiO2. Thereafter, a thin layer of a barrier metal, such as Ti, TiW or TiN, may be provided on top of the insulating layer and within the trough and/or contact to act as a diffusion barrier to prevent inter-diffusion of subsequently deposited metal the metal into the silicon, and between such metal and the oxide forming the contact or trench. After barrier metal deposition, a layer of copper is deposited to completely fill the trench or contact.
Despite the availability of these techniques, there remains a need for a copper metallization process for fabricating interconnects at high levels of integration. Such highly integrated interconnects must provide void-free vias, particularly in high aspect ratio, sub-quarter micron wide apertures for forming lines contacts and vias. Furthermore, there is a need for a process providing a circuit with higher electrical conductivity and improved electromigration resistance. It would be desirable to have a simple process requiring fewer processing steps to form metal plugs in the vias and wires in the trenches. It would be further desirable if the process could achieve all this without the use of metal etch techniques.
The present invention provides a method for forming a dual damascene interconnect in a dielectric layer having dual damascene via and wire definitions, wherein the via has a floor exposing a deposition enhancing material. The method includes selective chemical vapor deposition of a conductive metal, preferably aluminum, on the deposition enhancing material of the via floor to form a plug in the via. A barrier layer is then deposited over the exposed surfaces of the plug and wire definition. The wire definition is then filled by depositing a conductive metal, preferably copper, over the barrier layer. Finally, the conductive metal, the barrier and the dielectric layers are planarized, such as by chemical mechanical polishing, to define a conductive wire.
Another aspect of the invention provides a method of forming a dual damascene interconnect module over a deposition enhancing material. This method further includes the steps of forming a dielectric layer over the deposition enhancing material and then etching the dielectric layer to form a dual damascene via and wire definition, wherein the via has a floor exposing a deposition enhancing material. Where a substrate does not already have a layer of a deposition enhancing material, this layer may be provided prior to forming the dielectric layer. Furthermore, a multilevel metal interconnect may be formed in accordance with the invention by depositing a subsequent barrier layer of a deposition enhancing material over the planarized layers. A dielectric layer is subsequently formed and filled by repeating the steps described above.